AT32AP7001_1 Datasheet, PDF (743/829 Pages) ATMEL Corporation – AVR32 32-bit Microcontroller

AT32AP7001
Table 35-3.
RGB 5:6:5
RGB Format in Default Mode, RGB_CFG = 00, No Swap
Byte 0
R4(i)
R3(i)
R2(i)
R1(i)
Byte 1
G2(i)
G1(i)
G0(i)
B4(i)
Byte 2
R4(i+1) R3(i+1) R2(i+1) R1(i+1)
Byte 3
G2(i+1) G1(i+1) G0(i+1) B4(i+1)
R0(i)
B3(i)
R0(i+1)
B3i+1)
G5(i)
B2(i)
G5(i+1)
B2(i+1)
G4(i)
B1(i)
G4(i+1)
B1(i+1)
G3(i)
B0(i)
G3(i+1)
B0(i+1)
Table 35-4.
Mode
RGB 5:6:5
RGB Format, RGB_CFG = 10 (Mode 2), No Swap
Byte
D7
D6
D5
D4
Byte 0
G2(i)
G1(i)
G0(i)
R4(i)
Byte 1
B4(i)
B3(i)
B2(i)
B1(i)
Byte 2
G2(i+1) G1(i+1) G0(i+1) R4(i+1)
Byte 3
B4(i+1) B3(i+1) B2(i+1) B1(i+1)
D3
R3(i)
B0(i)
R3(i+1)
B0(i+1)
D2
R2(i)
G5(i)
R2(i+1)
G5(i+1)
D1
R1(i)
G4(i)
R1(i+1)
G4(i+1)
D0
R0(i)
G3(i)
R0(i+1)
G3(i+1)
Table 35-5.
Mode
RGB 8:8:8
RGB 5:6:5
RGB Format in Default Mode, RGB_CFG = 00, Swap Activated
Byte
D7
D6
D5
D4
D3
Byte 0
R0(i)
R1(i)
R2(i)
R3(i)
R4(i)
Byte 1
G0(i)
G1(i)
G2(i)
G3(i)
G4(i)
Byte 2
B0(i)
B1(i)
B2(i)
B3(i)
B4(i)
Byte 3
R0(i+1) R1(i+1) R2(i+1) R3(i+1) R4(i+1)
Byte 0
G3(i)
G4(i)
G5(i)
R0(i)
R1(i)
Byte 1
B0(i)
B1(i)
B2(i)
B3(i)
B4(i)
Byte 2
G3(i+1) G4(i+1) G5(i+1) R0(i+1) R1(i+1)
Byte 3
B0(i+1) B1(i+1) B2(i+1) B3(i+1) B4(i+1)
D2
R5(i)
G5(i)
B5(i)
R5(i+1)
R2(i)
G0(i)
R2(i+1)
G0(i+1)
D1
R6(i)
G6(i)
B6(i)
R6(i+1)
R3(i)
G1(i)
R3(i+1)
G1(i+1)
D0
R7(i)
G7(i)
B7(i)
R7(i+1)
R4(i)
G2(i)
R4(i+1)
G2(i+1)
The RGB 5:6:5 input format is processed to be displayed as RGB 5:5:5 format.
35.5.3 Clocks
The sensor master clock (MCK) can be generated either by the power manager through a pro-
grammable clock output or by an external oscillator connected to the sensor.
None of the sensors embeds a power management controller, so providing the clock by the
power manager is a simple and efficient way to control power consumption of the system.
Care must be taken when programming the system clock. The ISI has two clock domains, the
system bus clock and the pixel clock provided by sensor. The two clock domains are not syn-
chronized, but the system clock must be faster than pixel clock.
32015G–AVR32–09/09
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