AT32AP7001_1 Datasheet, PDF (718/829 Pages) ATMEL Corporation – AVR32 32-bit Microcontroller

AT32AP7001
- If the waveform is left aligned, then the output waveform period depends on the counter
source clock and can be calculated:
By using the Master Clock (MCK) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024), the resulting period formula will be:
(_---X_-----×_-----C_----P_----R_----D_-----)
MCK
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
(_---C_----R_----P_----D_------×_-----D_-----I_--V_----A_----)_{- or} (_---C_----R_----P_----D_------×_-----D_-----I_--V_----A_----B_----)_-
MCK
MCK
If the waveform is center aligned then the output waveform period depends on the counter
source clock and can be calculated:
By using the Master Clock (MCK) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will
be:
(_---2_-----×_-----X_-----×_-----C_----P_----R_----D_-----)
MCK
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
(_---2_-----×_-----C_----P_----R_----D_------×_-----D_----I_---V_----A_----) _or (_---2_-----×_-----C_----P_----R_----D_------×_-----D_----I_---V_----B_----)
MCK
MCK
• the waveform duty cycle. This channel parameter is defined in the CDTY field of the CDTYx
register.
If the waveform is left aligned then:
duty cycle = ⁽---^p---^e---^r---ⁱ--^o---^d-----–----¹-----^⁄---^f-^c---^h----^a---ⁿ---ⁿ----^e---^l-^_----^x---^_---^c---^l-^o----^c---^k----^×-----^C----^D-----^T----^Y----⁾
period
If the waveform is center aligned, then:
duty cycle = -⁽--⁽--^p----^e---^r--ⁱ--^o----^d----^⁄---²----⁾---–-----¹----^⁄--₍-^f--^c_p---^h_e---^a_r---_iⁿ--_o--ⁿ-_d--^e---_⁄^l--^_2---^x-₎--^_---^c---^l--^o---^c---^k----^×-----^C-----^D----^T----^Y----⁾---⁾
• the waveform polarity. At the beginning of the period, the signal can be at high or low level.
This property is defined in the CPOL field of the CMRx register. By default the signal starts by
a low level.
• the waveform alignment. The output waveform can be left or center aligned. Center aligned
waveforms can be used to generate non overlapped waveforms. This property is defined in the
CALG field of the CMRx register. The default mode is left aligned.
32015G–AVR32–09/09
718