AT32AP7001_1 Datasheet, PDF (355/829 Pages) ATMEL Corporation – AVR32 32-bit Microcontroller

AT32AP7001
Figure 24-8. Transmitter Block Diagram
TFMR.DATDEF
TX_FRAME_SYNC
RX_FRAME_SYNC
Transmitter Clock _Start
Selector
1
TFMR.MSBF
0
Transmit Shift Register
TFMR.FSDEN
TCMR.STTDLY
01
TFMR.DATLEN
THR
TSHR
CR.TXEN
SR.TXEN
CR.TXDIS
TCMR.STTDLY
TFMR.FSDEN
TFMR.DATNB
TFMR.FSLEN
TX_DATA
24.7.3
Receiver Operations
A received frame is triggered by a start event and can be followed by synchronization data
before data transmission.
The start event is configured setting the Receive Clock Mode Register (RCMR). See Section
“24.7.4” on page 356.
The frame synchronization is configured setting the Receive Frame Mode Register (RFMR). See
Section “24.7.5” on page 358.
The receiver uses a shift register clocked by the receiver clock signal and the start mode
selected in the RCMR. The data is transferred from the shift register depending on the data for-
mat selected.
When the receiver shift register is full, the SSC transfers this data in the holding register, the sta-
tus flag RXRDY is set in SR and the data can be read in the receiver holding register. If another
transfer occurs before read of the RHR register, the status flag OVERUN is set in SR and the
receiver shift register is transferred in the RHR register.
32015G–AVR32–09/09
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