AT32AP7001_1 Datasheet, PDF (526/829 Pages) ATMEL Corporation – AVR32 32-bit Microcontroller

AT32AP7001
28.7.3 Cycle Register
Register Name:
Access Type:
Offset:
Reset Value:
CYCLE
Read/Write
0x08 + CS_number*0x10
0x00030003
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
NRDCYCLE[8]
23
22
21
20
19
18
17
16
NRDCYCLE[7:0]
15
14
13
12
11
10
–
–
–
–
–
–
9
8
–
NWECYCLE[8]
7
6
5
4
3
2
1
0
NWECYCLE[7:0]
• NRDCYCLE[8:0]: Total Read Cycle Length
The total read cycle length is the total duration in clock cycles of the read cycle. It is equal to the sum of the setup, pulse and
hold steps of the NRD and NCS signals. It is defined as:
Read Cycle Length = (256 × NRDCYCLE[8:7] + NRDCYCLE[6:0]) clock cycles
• NWECYCLE[8:0]: Total Write Cycle Length
The total write cycle length is the total duration in clock cycles of the write cycle. It is equal to the sum of the setup, pulse and
hold steps of the NWE and NCS signals. It is defined as:
Write Cycle Length = (256 × NWECYCLE[8:7] + NWECYCLE[6:0]) clock cycles
32015G–AVR32–09/09
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