SAM7S16_14 Datasheet, PDF (730/775 Pages) ATMEL Corporation – Internal High-speed Flash

40.22.6.8 SPI: Disable Issue
The SPI Command “SPI Disable” is not possible during a transfer, it must be performed only after TX_EMPTY ris-
ing else there is everlasting dummy transfers occur.
Problem Fix/Workaround
None.
40.22.6.9 SPI: Software Reset and SPIEN Bit
The SPI Command “software reset” does not reset the SPIEN config bit. Therefore rewriting an SPI enable com-
mand does not set TX_READY, TX_EMPTY flags.
Problem Fix/Workaround
Send SPI disable command after a software reset.
40.22.6.10 SPI: CSAAT = 1 and Delay
If CSAAT = 1 for current access and there is no more TX request for a time greater than DLYBCT + DLYBCS, then
if an access is requested on another slave, the NPCS bus switches from one CS to the one requested without
DLYBCS. External Slaves may reach a contention on SPI_MISO line for a short period.
Problem Fix/Workaround
Assert the Last Transfer Command (NPCS de-activation) for the last character of each slave.
40.22.6.11 SPI: Bad Serial Clock Generation on 2nd Chip Select
Bad Serial clock generation on the 2nd chip select when SCBR = 1, CPOL = 1 and NCPHA = 0.
This occurs using SPI with the following conditions:
• Master Mode
• CPOL = 1 and NCPHA = 0
• Multiple chip selects are used with one transfer with Baud rate (SCBR) equal to 1 (i.e., when serial clock
frequency equals the system clock frequency) and the other transfers set with SCBR are not equal to 1
• Transmitting with the slowest chip select and then with the fastest one, then an additional pulse is generated
on output SPCK during the second transfer.
Problem Fix/Workaround
Do not use a multiple Chip Select configuration where at least one SCRx register is configured with SCBR = 1 and
the others differ from 1 if NCPHA = 0 and CPOL = 1.
If all chip selects are configured with Baudrate = 1, the issue does not appear.
40.22.7 Synchronous Serial Controller (SSC)
40.22.7.1 SSC: Periodic Transmission Limitations in Master Mode
If the Least Significant Bit is sent first (MSBF = 0), the first TAG during the frame synchro is not sent.
Problem Fix/Workaround
None.
40.22.7.2 SSC: Transmitter Limitations in Slave Mode
If TK is programmed as output and TF is programmed as input, it is impossible to emit data when the start of edge
(rising or falling) of synchro has a Start Delay equal to zero.
Problem Fix/Workaround
None.
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
730