SAM7S16_14 Datasheet, PDF (632/775 Pages) ATMEL Corporation – Internal High-speed Flash

Constraints on the transmitter device connected to the SAM7S USART receiver side:
The transmitter may use the timeguard feature or send two STOP conditions. Only one STOP condition is taken
into account by the receiver state machine. After this STOP condition, as there is no valid data, the receiver state
machine will go in idle mode and enable the RXBRK flag.
40.7.11.5 USART: DCD is active High instead of Low
The DCD signal is active at High level in the USART Modem Mode.
DCD should be active at Low level.
Problem Fix/Workaround
Add an inverter.
40.7.12 Voltage Regulator
40.7.12.1 Voltage Regulator: Current Consumption in Deep Mode
Current consumption in Deep Mode is maximum 60 µA instead of 25 µA.
Due to current rejection from VDDIN to VDDCORE, the current consumption in Deep Mode cannot be guaranteed.
Instead, 60 µA is guaranteed whatever the condition.
Problem Fix/Workaround
None.
40.7.12.2 Voltage Regulator: Load Versus Temperature
Maximum load is 50 mA at 85 °C (instead of 100 mA).
Maximum load is 100 mA at 70°C.
Problem Fix/Workaround
None.
40.7.13 Watchdog Timer (WDT)
40.7.13.1 WDT: The Watchdog Timer May Lock the Device in a Reset State
Under certain rare circumstances, if the Watchdog Timer is used with the Watchdog Reset enabled (WDRSTEN
set at 1), the Watchdog Timer may lock the device in a reset state when the user restarts the watchdog
(WDDRSTT). The only way to recover from this state is a power-on reset. The issue depends on the values of
WDD and WDV in the WDT_MR register.
Problem Fix/Workaround
Two workarounds are possible.
1. Either do not use the Watchdog Timer with the Watchdog Reset enabled (WDRSTEN set at 1),
2. or set WDD to 0xFFF and in addition use only one of the following values for WDV: 0xFFF, 0xDFF, 0xBFF,
0x9FF, 0x7FF, 0x77F, 0x6FF, 0x67F, 0x5FF, 0x57F, 0x4FF, 0x47F, 0x3FF, 0x37F, 0x2FF, 0x27F, 0x1FF,
0x1BF, 0x17F, 0x13F, 0x0FF, 0x0DF, 0x0BF, 0x09F, 0x07F, 0x06F, 0x05F, 0x04F, 0x03F, 0x037, 0x02f,
0x027, 0x01F, 0x01B, 0x017, 0x013 and 0x00F.
40.7.13.2 WDT: The Watchdog Timer Status Register and Interrupt
Under certain rare circumstances, if the Watchdog Timer is used with the Watchdog Fault Interrupt enabled
(WDFIEN set at 1), the Watchdog Timer may trigger the interrupt (wdt_fault) erroneously. The Watchdog Timer
Status Register may be wrong also (WDERR and WDUNF). The issue depends on the values of WDD and WDV in
the WDT_MR register.
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
632