SAM7S16_14 Datasheet, PDF (306/775 Pages) ATMEL Corporation – Internal High-speed Flash

Figure 29-16. TWI Read Operation with Single Data Byte without Internal Address
BEGIN
Set TWI clock
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
(Needed only once)
Set the Control register:
- Master enable
TWI_CR = MSEN
Set the Master Mode register:
- Device slave address
- Transfer direction bit
Read ==> bit MREAD = 1
Start the transfer
TWI_CR = START | STOP
Read status register
No
RXRDY = 1?
Yes
Read Receive Holding Register
Read Status register
No
TXCOMP = 1?
Yes
END
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
306