SAM7S16_14 Datasheet, PDF (297/775 Pages) ATMEL Corporation – Internal High-speed Flash

high. The output stages of devices connected to the bus must have an open-drain or open-col-
lector to perform the wired-AND function.
TWD and TWCK pins may be multiplexed with PIO lines. To enable the TWI, the programmer
must perform the following steps:
• Program the PIO controller to:
– Dedicate TWD and TWCK as peripheral lines.
– Define TWD and TWCK as open-drain.
29.5.2
Power Management
• Enable the peripheral clock.
The TWI interface may be clocked through the Power Management Controller (PMC), thus the
programmer must first configure the PMC to enable the TWI clock.
29.5.3 Interrupt
The TWI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). In
order to handle interrupts, the AIC must be programmed before configuring the TWI.
29.6 Functional Description
29.6.1
Transfer format
The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must
be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure
29-4 on page 297).
Each transfer begins with a START condition and terminates with a STOP condition (see Figure
29-3 on page 297).
• A high-to-low transition on the TWD line while TWCK is high defines the START condition.
• A low-to-high transition on the TWD line while TWCK is high defines a STOP condition.
Figure 29-3. START and STOP Conditions
TWD
TWCK
Start
Stop
Figure 29-4. Transfer Format
TWD
TWCK
Start Address R/W Ack
29.6.2
Modes of Operation
The TWI has two modes of operation:
Data
Ack
Data
Ack Stop
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
297