SAM7S16_14 Datasheet, PDF (62/775 Pages) ATMEL Corporation – Internal High-speed Flash

13.3.4.3 Brownout Reset
When the brown_out/bod_reset signal is asserted, the Reset State Manager immediately enters the Brownout
Reset. In this state, the processor, the peripheral and the external reset lines are asserted.
The Brownout Reset is left Y Slow Clock cycles after the rising edge of brown_out/bod_reset after a two-cycle
resynchronization. An external reset is also triggered.
When the processor reset is released, the field RSTTYP in RSTC_SR is loaded with the value 0x5, thus indicating
that the last reset is a Brownout Reset.
Figure 13-6. Brownout Reset State
SLCK
MCK
Any
Freq.
brown_out
or bod_reset
proc_nreset
RSTTYP
Any
periph_nreset
Resynch.
2 cycles
Processor Startup
= 3 cycles
XXX
0x5 = Brownout Reset
NRST
(nrst_out)
EXTERNAL RESET LENGTH
8 cycles (ERSTL=2)
SAM7S Series [DATASHEET] 62
6175M–ATARM–26-Oct-12