AT24C16D_14 Datasheet, PDF (7/27 Pages) ATMEL Corporation – IC-Compatible (2-Wire) Serial EEPROM

4. Memory Organization
The AT24C16D is internally organized as 128 pages of 16 bytes each.
4.1 Device Addressing
Accessing the device requires an 8-bit Device Address word following a Start condition to enable the device for
a Read or Write operation. Since multiple slave devices can reside on the serial bus each slave device must
have its own unique address so the Master can access each device independently.
The most significant four bits of the Device Address word is referred to as the device type identifier. The device
type identifier ‘1010’ (Ah) is required in bits 7 through 4 of the Device Address byte (see Table 4-1).
Following the four bit device type identifier in the bit 3, bit 2, and bit 1 position of the Device Address byte are
bits A10, A9, and A8 which are the three most significant bits of the memory array word address. The eighth bit
(bit 0) of the Device Address byte is the Read/Write operation select bit. A Read operation is initiated if this bit is
high, and a Write operation is initiated if this bit is low. Please refer to Table 4-1 to review these bit positions.
Upon the successful comparison of the Device Address byte, the EEPROM will return an ACK. If a valid
comparison is not made, the device will NACK and return to a standby state.
Table 4-1. Device Address Byte
Package
Bit 7
Device Type Identifier
Bit 6
Bit 5
Bit 4
Most Significant Bits
of the Word Address
Bit 3
Bit 2
Bit 1
Read/
Write
Bit 0
All Package Types
1
0
1
0
A10
A9
A8
R/W
For all operations except the Current Address Read, a Word Address byte must be transmitted to the device
immediately following the Device Address byte. The Word Address byte consists of the remaining eight bits of
the 11-bit memory array word address, and is used to specify which byte location in the EEPROM to start
reading or writing. Please refer to Table 4-2 to review these bit positions.
Table 4-2. Word Address Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
A7
A6
A5
A4
A3
A2
A1
A0
The relationship of the AC timing parameters with respect to SCL and SDA for the AT24C16D are shown in the
timing waveform Figure 8-1 on page 14. The AC timing characteristics and specifications are outlined in Section
8.4 “AC Characteristics” on page 14.
AT24C16D [PRELIMINARY DATASHEET]
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Atmel-8906A-SEEPROM-AT24C16D-Datasheet_042014