AT24C16D_14 Datasheet, PDF (10/27 Pages) ATMEL Corporation – IC-Compatible (2-Wire) Serial EEPROM

Figure 5-4. Write Cycle Timing
SCL
8
Data Word n
SDA
D0
9
ACK
Stop
Condition
9
ACK
First Acknowledge from the device
to a valid device address sequence after
t_WR
write cycle is initiated. The minumum t_WR
can only be determined through
Start
the use of an ACK Polling routine.
Stop
Condition
Condition
5.5 Write Protection
The AT24C16D utilizes a hardware data protection scheme that allows the user to write protect the entire
memory contents when the WP pin is at V_CC (or a valid V_IH). No write protection will be set if the WP pin is at
GND or left floating.
Table 5-1. AT24C16D Write Protect Behavior
WP Pin Voltage
Part of the Array Protected
V_CC
GND
Full Array
None — Write Protection Not Enabled
The status of the WP pin is sampled at the Stop condition for every Byte Write or Page Write command prior to
the start of an internally self-timed Write operation. Changing the WP pin state after the Stop condition has been
sent will not alter or interrupt the execution of the write cycle. The WP pin state must be valid with respect to the
associated setup (t_SU.WP) and hold (t_HD.WP) timing as shown in the Figure 5-5 below. The WP setup time is the
amount of time that the WP state must be stable before the Stop condition is issued. The WP hold time is the
amount of time after the Stop condition that the WP must remain stable.
If an attempt is made to write to the device while the WP pin has been asserted, the device will acknowledge the
Device Address, Word Address, and Data bytes but no write cycle will occur when the Stop condition is issued,
and the device will immediately be ready to accept a new Read or Write command.
Figure 5-5. Write Protect Setup and Hold Timing
SCL
SDA IN
WP
1
2
7
8
Data Word Input Sequence Page/Byte Write Operation
D7
D6
D1
D0
9
Stop
by
Master
ACK by Slave
t_SU.WP t_HD.WP
10 AT24C16D [PRELIMINARY DATASHEET]
Atmel-8906A-SEEPROM-AT24C16D-Datasheet_042014