AT24C16D_14 Datasheet, PDF (12/27 Pages) ATMEL Corporation – IC-Compatible (2-Wire) Serial EEPROM

Figure 6-2. Random Read
SCL
SDA
Start
by
Master
12 3 4 567 89 12 345 67 89
Device Address Byte
Word Address Byte
10
MSB
1 0 A10 A9 A8 0
0 A7 A6 A5 A4 A3 A2 A1 A0 0
MSB
ACK
from
Slave
ACK
from
Slave
Dummy Write
12 3 4 567 89 12 345 67 89
Start
by
Master
Device Address Byte
Data Word (n)
1 0 1 0 X X X 1 0 D7 D6 D5 D4 D3 D2 D1 D0 1
MSB
MSB
ACK
from
Slave
NACK
from
Master
Stop
by
Master
6.3 Sequential Read
Sequential Reads are initiated by either a Current Address Read or a Random Read. After the bus Master
receives a data word, it responds with an acknowledge. As long as the EEPROM receives an ACK, it will
continue to increment the word address and serially clock out sequential data words. When the maximum
memory address is reached, the data word address will roll-over and the sequential read will continue from the
beginning of the memory array. All types of Read operations will be terminated if the bus Master does not
respond with an ACK (it NACKs) during the ninth clock cycle. A Read instruction may be terminated at any point
with a Stop condition which will force the device into standby mode.
Figure 6-3. Sequential Read
SCL
12 3 4 567 89 12 345 67 89
Device Address Byte
Data Word (n)
SDA
Start
by
Master
10
MSB
1 0 A10 A9 A8 1 0 D7 D6 D5 D4 D3 D2 D1 D0 0
MSB
ACK
from
Slave
ACK
from
Master
12 3 4 567 89 12 345 67 89 123 45 67 89
Data Word (n+1)
Data Word (n+2)
Data Word (n+x)
D7 D6 D5 D4 D3 D2 D1 D0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 D7 D6 D5 D4 D3 D2 D1 D0 1
MSB
MSB
MSB
ACK
from
Master
ACK
from
Master
NACK
from
Master
Stop
by
Master
7. Device Default Condition from Atmel
The AT24C16D is delivered with the EEPROM array set to Logic 1, resulting in FFh data in all locations.
12 AT24C16D [PRELIMINARY DATASHEET]
Atmel-8906A-SEEPROM-AT24C16D-Datasheet_042014