AT91SAM9261 Datasheet, PDF (674/688 Pages) ATMEL Corporation – ARM926EJ-S BASED MICROCONTROLLER

Table 42-1.
Doc. Rev.
6062D
Revision History (Continued)
Date
14-Apr-06
Comments
PMC: Updated OUTx bit descriptions in Section 25.10.9 ”PMC Clock Generator PLL A
Register” on page 270 and Section 25.10.10 ”PMC Clock Generator PLL B Register”
on page 271.
PMC: Added note defining PIDx in Section 25.10.4 ”PMC Peripheral Clock Enable
Register” on page 266, Section 25.10.5 ”PMC Peripheral Clock Disable Register” on
page 266 and Section 25.10.6 ”PMC Peripheral Clock Status Register” on page 267.
PMC: Updated document to with details on oscillator selection. Added bit OSCSEL to
Section 25.10.15 ”PMC Status Register” on page 275.
PMC: Addition of PLL Charge Pump Current Register in Table 25-3, “Register
Mapping,” on page 262 and Section 25.10.17 ”PLL Charge Pump Current Register” on
page 277.
AIC: Section 26.7.3.1 ”Priority Controller” on page 285, incorrect reference of
SRCTYPE field to AIC_SVR register changed to AIC_SMR register.
AIC: Section 26.8 ”Advanced Interrupt Controller (AIC) User Interface” on page 292,
Table 26-2 added note in reference to PID2...PID31 bit fields.
AIC: Naming convention for AIC_FVR register harmonized in Table 26-2, “Register
Mapping,” on page 292 and ”Fast Forcing” on page 289.
DBGU: In Figure 27-1, “Debug Unit Functional Block Diagram,” on page 304, changed
signal ice_reset to pad Power_on Reset. Also changed in bit description FNTRST in
Section 27.5.12 ”Debug Unit Force NTRST Register” on page 325.
USART: MANE bit removed from Section 31.7.3 ”USART Interrupt Enable Register”
on page 432.
USART: Section 31.5.1 ”I/O Lines” on page 402, text concerning TXD line added.
Table 31-3, “Binary and Decimal Values for Di,” on page 406 and Table 31-4, “Binary
and Decimal Values for Fi,” on page 406 DI and Fi properly referenced in titles.
Figure 31-24, “IrDA Demodulator Operations,” on page 422 modified.
TC: Addition of Table 33-1, “Timer Counter Clock Assignment,” on page 483.
TC: Section 33.5.12 ”External Event/Trigger Conditions” on page 496 new text as
follows: “....(EEVT = 0), TIOB is no longer used as an output and the compare register
B is not used to generate waveforms and subsequently no IRQs.” Added note ⁽¹⁾ to
EEVT bit description in Section 33.6.5 ”TC Channel Mode Register: Waveform Mode”
on page 504.
MCI: Specified reset condition for DCRCE and DTOE bits in Section 34.9.10 ”MCI
Status Register” on page 538.
MCI: Update to Figure 34-9, “Write Functional Flow Diagram,” on page 525 in case of
write with PDC. Addition of Figure 34-10, “Multiple Write Functional Flow Diagram,” on
page 526.
UHP: Corrected signal name and corrected ASB bus to ASB bus in Figure 35-1,
“Block Diagram,” on page 545 to UHPCK.
LCDC: Corrected typos in signal names in Figure 37-4, “TFT Panel Timing, CLKMOD
= 0, VPW = 2, VBP = 2, VFP = 1,” on page 598.
LCDC: Removed references to AHB and LCDC clock domains in Figure 37-1, “LCD
Macrocell Block Diagram,” on page 586.
LCDC: Updated Section 37.9 ”Register Configuration Guide” on page 610.
Change
Request
Ref.
2467
2468
2558
2568
2512
2548
2524
2747
2794
2470
2704
2593
2462
2924
2402
2424
2426
674 AT91SAM9261 Preliminary
6062F–ATARM–05-Dec-06