AT91SAM9261 Datasheet, PDF (247/688 Pages) ATMEL Corporation – ARM926EJ-S BASED MICROCONTROLLER

AT91SAM9261 Preliminary
When disabling the main oscillator by clearing the MOSCEN bit in CKGR_MOR, the MOSCS
bit in PMC_SR is automatically cleared, indicating the main clock is off.
When enabling the main oscillator, the user must initiate the main oscillator counter with a
value corresponding to the startup time of the oscillator. This startup time depends on the
crystal frequency connected to the main oscillator.
When the MOSCEN bit and the OSCOUNT are written in CKGR_MOR to enable the main
oscillator, the MOSCS bit in PMC_SR (Status Register) is cleared and the counter starts
counting down on the slow clock divided by 8 from the OSCOUNT value. Since the
OSCOUNT value is coded with 8 bits, the maximum startup time is about 62 ms.
When the counter reaches 0, the MOSCS bit is set, indicating that the main clock is valid. Set-
ting the MOSCS bit in PMC_IMR can trigger an interrupt to the processor.
24.3.4
Main Clock Frequency Counter
The Main Oscillator features a Main Clock frequency counter that provides the quartz fre-
quency connected to the Main Oscillator. Generally, this value is known by the system
designer; however, it is useful for the boot program to configure the device with the correct
clock speed, independently of the application.
The Main Clock frequency counter starts incrementing at the Main Clock speed after the next
rising edge of the Slow Clock as soon as the Main Oscillator is stable, i.e., as soon as the
MOSCS bit is set. Then, at the 16th falling edge of Slow Clock, the MAINRDY bit in
CKGR_MCFR (Main Clock Frequency Register) is set and the counter stops counting. Its
value can be read in the MAINF field of CKGR_MCFR and gives the number of Main Clock
cycles during 16 periods of Slow Clock, so that the frequency of the crystal connected on the
Main Oscillator can be determined.
24.3.5
Main Oscillator Bypass
The user can input a clock on the device instead of connecting a crystal. In this case, the user
has to provide the external clock signal on the XIN pin. The input characteristics of the XIN pin
under these conditions are given in the product electrical characteristics section. The program-
mer has to be sure to set the OSCBYPASS bit to 1 and the MOSCEN bit to 0 in the Main OSC
register (CKGR_MOR) for the external clock to operate properly.
24.4
Divider and PLL Block
The PLL embeds an input divider to increase the accuracy of the resulting clock signals. How-
ever, the user must respect the PLL minimum input frequency when programming the divider.
Figure 24-4 shows the block diagram of the divider and PLL blocks.
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