AT91SAM9261 Datasheet, PDF (588/688 Pages) ATMEL Corporation – ARM926EJ-S BASED MICROCONTROLLER

FIFO
Serializer
The datapath can be characterized by two parameters: initial_latency and cycles_per_data. The
parameter initial_latency is defined as the number of LCDC Core Clock cycles until the first data
is available at the output of the datapath. The parameter cycles_per_data is the minimum num-
ber of LCDC Core clock cycles between two consecutive data at the output interface.
These parameters are different for the different configurations of the LCD Controller and are
shown in Table 37-2.
Table 37-2. Datapath Parameters
Configuration
DISTYPE
SCAN
IFWIDTH
TFT
STN Mono
Single
4
STN Mono
Single
8
STN Mono
Dual
8
STN Mono
Dual
16
STN Color
Single
4
STN Color
Single
8
STN Color
Dual
8
STN Color
Dual
16
initial_latency
9
13
17
17
25
11
12
14
15
cycles_per_data
1
4
8
8
16
2
3
4
6
The FIFO block buffers the input data read by the DMA module. It contains two input FIFOs to
be used in Dual Scan configuration that are configured as a single FIFO when used in single
scan configuration.
The size of the FIFOs allows a wide range of architectures to be supported.
The upper threshold of the FIFOs can be configured in the FIFOTH field of the LCDFIFO regis-
ter. The LCDC core will request a DMA transfer when the number of words in each FIFO is less
than FIFOTH words. To avoid overwriting in the FIFO and to maximize the FIFO utilization, the
FIFOTH should be programmed with:
FIFOTH = 512 words - (2 x DMA_BURST_LENGTH + 3)
where:
• 512 words is the effective size of the FIFO. It is the total FIFO memory size in single scan
mode and half that size in dual scan mode.
• DMA_burst_length is the burst length of the transfers made by the DMA
This block serializes the data read from memory. It reads words from the FIFO and outputs pix-
els (1 bit, 2 bits, 4 bits, 8 bits, 16 bits or 24 bits wide) depending on the format specified in the
PIXELSIZE field of the LCDCON2 register. It also adapts the memory-ordering format. Both big-
endian and little-endian formats are supported. They are configured in the MEMOR field of the
LCDCON2 register.
The organization of the pixel data in the memory depends on the configuration and is shown in
Table 37-3 and Table 37-4.
588 AT91SAM9261 Preliminary
6062F–ATARM–05-Dec-06