AT91SAM9261 Datasheet, PDF (666/688 Pages) ATMEL Corporation – ARM926EJ-S BASED MICROCONTROLLER

41.2.7.3
TWI: NACK Status Bit Lost
During a master frame, if TWI_SR is read between the Non Acknowledge condition detection
and the TXCOMP bit rising in the TWI_SR, the NACK bit is not set.
Problem Fix/Workaround
The user must wait for the TXCOMP status bit by interrupt and must not read the TWI_SR as
long as transmission is not completed.
Note: TXCOMP and NACK fields are set simultaneously and the NACK field is reset after the read of
the TWI_SR.
41.2.7.4
TWI: Possible Receive Holding Register Corruption
When loading the TWI_RHR, the transfer direction is ignored. The last data byte received in
the TWI_RHR is corrupted at the end of the first subsequent transmit data byte. Neither
RXRDY nor OVERRUN status bits are set if this occurs.
Problem Fix/Workaround
The user must be sure that received data is read before transmitting any new data.
41.2.7.5
TWI: Software reset
When a software reset is performed during a frame and when TWCK is low, it is impossible to
initiate a new transfer in READ or WRITE mode.
Problem Fix/Workaround
None.
41.2.7.6
TWI: STOP not generated
If the sequence described as follows occurs:
1. WRITE 1 or more bytes at a given address.
2. Send a STOP.
3. Wait for TXCOMP flag.
4. READ (or WRITE) 1 or more bytes at the same address.
then STOP is not generated.
The line will show : DADR BYTE 1, ..., BYTE n, NO STOP generated, BYTE 1, ..., BYTE n.
Problem Fix/Workaround
Insert a delay of one TWI clock period before step 4 in the sequence above.
41.2.8 USART
41.2.8.1
USART: CTS signal in Hardware Handshake
When Hardware Handshaking is used and if CTS goes low near the end of the starting bit of
the transmitter, a character is lost.
Problem Fix/Workaround
CTS must not go low during a time slot comprised between 2 Master Clock periods before the
rising edge of the starting bit and 16 Master Clock periods after the rising edge of the starting
bit.
666 AT91SAM9261 Preliminary
6062F–ATARM–05-Dec-06