SAM7S321_14 Datasheet, PDF (616/775 Pages) ATMEL Corporation – ARM-based Flash MCU

40.6.2.10 ADC: Spurious Clear of EOC Flag
If “x” and “y” are two successively converted channels and “z” is yet another enabled channel (“z” being neither “x”
nor “y”), reading CDR on channel “z” at the same instant as an end of conversion on channel “y” automatically
clears EOC[x] instead of EOC[z].
Problem Fix/Workaround
None.
40.6.2.11 ADC: Sleep Mode
If Sleep mode is activated while there is no activity (no conversion is being performed), it will take effect only after
a conversion occurs.
Problem Fix/Workaround
To activate sleep mode as soon as possible, it is recommended to write successively, ADC Mode Register
(SLEEP) then ADC Control Register (START bit field); to start an analog-to-digital conversion, in order put ADC
into sleep mode at the end of this conversion.
40.6.3 Master Clock (MCK)
40.6.3.1 MCK: Limited Master Clock Frequency Ranges
If the Flash is operating without wait states, the frequency of the Master Clock MCK must be lower than 3 MHz or
higher than 19 MHz.
If the Flash is operating with one wait state, the frequency of the Master Clock MCK must be lower than 3 MHz or
higher than 19 MHz.
If the Flash is operating with two wait states, the frequency of the Master Clock MCK must be lower than 3 MHz or
higher than 25 MHz.
If the Flash is operating with three wait states, the frequency of the Master Clock MCK must be lower than 3 MHz
or higher than 38 MHz.
If these constraints are not respected, the correct operation of the system cannot be guaranteed and either data or
prefetch abort might occur.
The maximum operating frequencies (at 30 MHz @ 0 Wait States and 55 MHz @ 1 Wait State) as stated in
Table 37-24, “Embedded Flash Wait States,” on page 582, are still applicable.
Note: It is not necessary to use 2 o 3 wait states because the Flash can operate at maximum frequency with only 1 wait state.
Problem Fix/Workaround
The user must ensure that the device is running at the authorized frequency by programming the PLL properly to
not run within the forbidden frequency range.
40.6.4 Non Volatile Memory Bits (NVM Bits)
40.6.4.1 NVM Bits: Write/Erase Cycles Number
The maximum number of write/erase cycles for Non Volatile Memory bits is 100. This includes Lock Bits (LOCKx),
General Purpose NVM bits (GPNVMx) and the Security Bit.
This maximum number of write/erase cycles is not applicable to 256 KB Flash memory, it remains at 10K for the
Flash memory.
Problem Fix/Workaround
None.
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
616