SAM7S321_14 Datasheet, PDF (287/775 Pages) ATMEL Corporation – ARM-based Flash MCU

28.7.5 SPI Status Register
Name:
SPI_SR
Access Type:
Read-only
31
30
29
–
–
–
23
22
21
–
–
–
15
14
13
–
–
–
7
TXBUFE
6
RXBUFF
5
ENDTX
28
–
20
–
12
–
4
ENDRX
27
–
19
–
11
–
3
OVRES
26
–
18
–
10
–
2
MODF
25
–
17
–
9
TXEMPTY
1
TDRE
24
–
16
SPIENS
8
NSSR
0
RDRF
• RDRF: Receive Data Register Full
0 = No data has been received since the last read of SPI_RDR
1 = Data has been received and the received data has been transferred from the serializer to SPI_RDR since the last read
of SPI_RDR.
• TDRE: Transmit Data Register Empty
0 = Data has been written to SPI_TDR and not yet transferred to the serializer.
1 = The last data written in the Transmit Data Register has been transferred to the serializer.
TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one.
• MODF: Mode Fault Error
0 = No Mode Fault has been detected since the last read of SPI_SR.
1 = A Mode Fault occurred since the last read of the SPI_SR.
• OVRES: Overrun Error Status
0 = No overrun has been detected since the last read of SPI_SR.
1 = An overrun has occurred since the last read of SPI_SR.
An overrun occurs when SPI_RDR is loaded at least twice from the serializer since the last read of the SPI_RDR.
• ENDRX: End of RX buffer
0 = The Receive Counter Register has not reached 0 since the last write in SPI_RCR⁽¹⁾ or SPI_RNCR⁽¹⁾.
1 = The Receive Counter Register has reached 0 since the last write in SPI_RCR⁽¹⁾ or SPI_RNCR⁽¹⁾.
• ENDTX: End of TX buffer
0 = The Transmit Counter Register has not reached 0 since the last write in SPI_TCR⁽¹⁾ or SPI_TNCR⁽¹⁾.
1 = The Transmit Counter Register has reached 0 since the last write in SPI_TCR⁽¹⁾ or SPI_TNCR⁽¹⁾.
• RXBUFF: RX Buffer Full
0 = SPI_RCR⁽¹⁾ or SPI_RNCR⁽¹⁾ has a value other than 0.
1 = Both SPI_RCR⁽¹⁾ and SPI_RNCR⁽¹⁾ have a value of 0.
• TXBUFE: TX Buffer Empty
0 = SPI_TCR⁽¹⁾ or SPI_TNCR⁽¹⁾ has a value other than 0.
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
287