SAM7S321_14 Datasheet, PDF (357/775 Pages) ATMEL Corporation – ARM-based Flash MCU

30.10.9 TWI Interrupt Mask Register
Name:
TWI_IMR
Access:
Read-only
Reset Value: 0x00000000
31
30
29
28
27
–
–
–
–
–
23
22
21
20
19
–
–
–
–
–
15
14
13
12
11
EOSACC
7
6
5
4
3
–
OVRE
GACC
SVACC
–
• TXCOMP: Transmission Completed Interrupt Mask
• RXRDY: Receive Holding Register Ready Interrupt Mask
• TXRDY: Transmit Holding Register Ready Interrupt Mask
• SVACC: Slave Access Interrupt Mask
• GACC: General Call Access Interrupt Mask
• OVRE: Overrun Error Interrupt Mask
• NACK: Not Acknowledge Interrupt Mask
• ARBLST: Arbitration Lost Interrupt Mask
• SCL_WS: Clock Wait State Interrupt Mask
• EOSACC: End Of Slave Access Interrupt Mask
0 = The corresponding interrupt is disabled.
1 = The corresponding interrupt is enabled.
26
–
18
–
10
SCL_WS
2
TXRDY
25
–
17
–
9
ARBLST
1
RXRDY
24
–
16
–
8
NACK
0
TXCOMP
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
357