SAM7S321_14 Datasheet, PDF (197/775 Pages) ATMEL Corporation – ARM-based Flash MCU

25.8 Clock Switching Details
25.8.1 Master Clock Switching Timings
Table 25-1 gives the worst case timings required for the Master Clock to switch from one selected clock to another
one. This is in the event that the prescaler is de-activated. When the prescaler is activated, an additional time of 64
clock cycles of the new selected clock has to be added.
Table 25-1. Clock Switching Timings (Worst Case)
From
Main Clock
SLCK
To
Main Clock
–
4 x SLCK +
2.5 x Main Clock
SLCK
PLL Clock
0.5 x Main Clock +
4.5 x SLCK
0.5 x Main Clock +
4 x SLCK +
PLLCOUNT x SLCK +
2.5 x PLLx Clock
–
2.5 x PLL Clock +
5 x SLCK +
PLLCOUNT x SLCK
PLL Clock
3 x PLL Clock +
4 x SLCK +
1 x Main Clock
3 x PLL Clock +
5 x SLCK
2.5 x PLL Clock +
4 x SLCK +
PLLCOUNT x SLCK
25.8.2 Clock Switching Waveforms
Figure 25-3. Switch Master Clock from Slow Clock to PLL Clock
Slow Clock
PLL Clock
LOCK
MCKRDY
Master Clock
Write PMC_MCKR
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
197