SAM7S321_14 Datasheet, PDF(601/775 Page) ATMEL Corporation – ARM-based Flash MCU

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

SAM7S321_14 Datasheet, PDF (601/775 Pages) ATMEL Corporation – ARM-based Flash MCU

◁

The maximum operating frequency with one Wait State (FWS = 1) is 48.1 MHz (instead of 55 MHz). Above 48.1

MHz and until 55 MHz, two Wait States (FWS = 2) are required.

Problem Fix/Workaround

Set the number of Wait States (FWS) according to the frequency requirements described in this errata.

40.4.3 Parallel Input/Output Controller (PIO)

40.4.3.1 PIO: Leakage on PA17 - PA20

When PA17, PA18, PA19 or PA20 (the I/O lines multiplexed with the analog inputs) are set as digital inputs with

pull-up disabled, the leakage can be 9 ÂµA in worst case and 90 nA in typical case per I/O when the I/O is set exter-

nally at low level.

Problem Fix/Workaround

Set the I/O to VDDIO by internal or external pull-up.

40.4.3.2 PIO: Electrical Characteristics on NRST and PA0-PA16 and PA21-31

When NRST or PA0-PA16 or PA21-PA31 are set as digital inputs with pull-up enabled, the voltage of the I/O stabi-

lizes at VPull-up.

Vpull-up

VPull-up Min

VDDIO - 0.65 V

VPull-up Max

VDDIO - 0.45 V

This condition causes a leakage through VDDIO. This leakage is 45 ÂµA per pad in worst case at 3.3 V and 25 ÂµA at

1.8V.

I Leakage

Parameter

I Leakage at 3,3V

I Leakage at 1.8V

Typ

2.5 ÂµA

1 ÂµA

Max

45 ÂµA

25 ÂµA

Problem Fix/Workaround

It is recommended to use an external pull-up if needed.

40.4.3.3 PIO: Drive Low NRST, PA0-PA16 and PA21-PA31

When NRST or PA0-PA16 and or PA21-PA31 are set as digital inputs with pull-up enabled, driving the I/O with an

output impedance higher than 500 ohms may not drive the I/O to a logical zero.

Problem Fix/Workaround

Output impedance must be lower than 500 ohms.

40.4.4 Pulse Width Modulation Controller (PWM)

40.4.4.1 PWM: Update when PWM_CCNTx = 0 or 1

If the Channel Counter Register value is 0 or 1, the Channel Period Register or Channel Duty Cycle Register is

directly modified when writing the Channel Update Register.

Problem Fix/Workaround

Check the Channel Counter Register before writing the update register.

SAM7S Series [DATASHEET]

6175MâATARMâ26-Oct-12

601

▷