U3600BM Datasheet, PDF (6/43 Pages) ATMEL Corporation – SINGLE CHIP CORDLESS TELEPHONE IC

Speed-up of the Loop
Filter of PLL3 (“1st. LO.”)
Similiar to PLL1, there is also a possibility to increase the locking speed of PLL3. This
can be done by setting the bit SU3. Having done this, the charge pump at the output of
the phase comparator has a bigger current capability and therefore charges the external
capacitors faster.
Adjustment of the
Modulator Gain
To fulfil the different requirements of the different countries three conversion gains of the
modulator are selectable by the bits GMOD [1:0] (R6: D2, D3).
Country settings see tables at channel frequencies and dividers. Ranges see electrical
characteristics at RF transmitter.
Modulator PLL
The fractional divider has been chosen to increase the reference frequency of the
modulator PLL.
557.5 kHz = f_Mod/ _èæP₁ + ₂--^Q--₂---¹₃--_øö
P₁: integer part of the fractional divider (M = 1)
Q₁: fractional part of the fractional divider (M = 1)
Q₁
=
223
´
æ
è
--------^f--^M----^o---^d---------
557.5 kHz
–
P_1øö
223
=
5_----5_---7_---._--5_-----k_---H_----z_--
2.5 kHz
The frequency step 2.5 kHz is a fraction of the reference frequency 557.5 kHz.
In fact, the fractional divider divides Q₁ times by (P₁ + 1) and (223 - Q₁) times by P₁
during 223 cycles.
®
-^Q----¹-----^´----⁽---^P----¹----+-----¹----⁾---+-----⁽---²---²---³-----–-----^Q-----¹---⁾--^P----¹-
223
=
P₁
+
--^Q-----¹--
223
Serial Bus Interface
For each comparison cycle (f_Ref1 = 557.5 kHz), the accumulator content is incremented
by the Q₁ value and the divider divides by the P₁ value. When the accumulator value
reaches or exceeds 223, the divider divides by the value (P₁ + 1). Then, the accumulator
holds the excess value (accumulator value - 223). After 223 cycles, the correct division
is executed.
The circuit is remoted by an external microcontroller through the serial bus.
The data is a 12-bit word:
A0 - A3: address of the destination register (0 to 15)
D7 - D0: contents of register
The data line must be stable when the clock is high and data must be serially shifted.
After 12 clock periods, the transfer to the destination register is (internally) generated by
a low to high transition of the data line when the clock is high.
6 U3600BM
4516C–CT0–08/02