U3600BM Datasheet, PDF (20/43 Pages) ATMEL Corporation – SINGLE CHIP CORDLESS TELEPHONE IC

Tables for Programming of the Dividers (Refer to Block Diagram)
Divider D1 for PLL2:
D11 (bit)
D10 (bit)
Decimally
D1 (Block Diagram),if M12 = 0
D1 (Block Diagram),if M12 = 1
0
0
0
2
1
0
1
1
8
4
1
0
2
6
3
1
1
3
4
2
Divider D2 between PLL1 and PLL2:
D20 (bit)
Decimally
0
0
0
1
D2 (Block Diagram),if M12 = 0
6
8
D2 (Block Diagram),if M12 = 1
3
4
Divider D3 for PLL1:
D31 (bit)
D30 (bit)
0
0
0
1
1
0
1
1
Decimally
0
1
2
3
D3 (Block Diagram)
1
2
6
4
Divider M for Reference
Frequency of PLL1:
There are several countries like Spain, the Netherlands and Portugal with relatively low
modulator frequencies fMod. In case of modulation there will be a big maximum time
shift between pulses coming from fractional divider and pulses coming from reference
frequency divider. As a consequence the phase comparator enters an undesired opera-
tion mode. To avoid entering this operation mode the reference frequency f_Ref1 has to be
reduced by a factor M. Simultaneously, keeping f_Mod constant, the factors of fractional
dividers have to be changed as well.
The connection between the additional reference frequency divider M and the factors P_M
and Q_M of fractional divider is given below. The subscript M denotes which value of M
refers to the factors P_M and Q_M of fractional divider. The formulas take into account that
the numerator of the fraction Q_M/223 must not exceed 223.
P_M = P₁ ´ M + integer (Q ´ M/223)
Q_M = Q₁ ´ M - 223 ´ integer (Q₁ ´ M/223)
20 U3600BM
4516C–CT0–08/02