SAM4S_14 Datasheet, PDF (567/1231 Pages) ATMEL Corporation – ARM-based Flash MCU

These additional modes are:
 Rising edge detection
 Falling edge detection
 Low-level detection
 High-level detection
In order to select an additional interrupt mode:
 The type of event detection (edge or level) must be selected by writing in the Edge Select register
(PIO_ESR) and Level Select register (PIO_LSR) which , respectively, the edge and level detection. The
current status of this selection is accessible through the Edge/Level Status register (PIO_ELSR).
 The polarity of the event detection (rising/falling edge or high/low-level) must be selected by writing in the
Falling Edge /Low-Level Select register (PIO_FELLSR) and Rising Edge/High-Level Select register
(PIO_REHLSR) which allow to select falling or rising edge (if edge is selected in PIO_ELSR) edge or high-
or low-level detection (if level is selected in PIO_ELSR). The current status of this selection is accessible
through the Fall/Rise - Low/High Status register (PIO_FRLHSR).
When an input edge or level is detected on an I/O line, the corresponding bit in the Interrupt Status register
(PIO_ISR) is set. If the corresponding bit in PIO_IMR is set, the PIO Controller interrupt line is asserted.The
interrupt signals of the 32 channels are ORed-wired together to generate a single interrupt signal to the interrupt
controller.
When the software reads PIO_ISR, all the interrupts are automatically cleared. This signifies that all the interrupts
that are pending when PIO_ISR is read must be handled. When an Interrupt is enabled on a “level”, the interrupt is
generated as long as the interrupt source is not cleared, even if some read accesses in PIO_ISR are performed.
Figure 31-7. Event Detector on Input Lines (Figure Represents Line 0)
Resynchronized input on line 0
Rising Edge
Detector
1
Falling Edge
0
Detector
0
PIO_REHLSR[0]
PIO_FRLHSR[0]
PIO_FELLSR[0]
1
High Level
1
Detector
Low Level
Detector
0
PIO_LSR[0]
PIO_ELSR[0]
PIO_ESR[0]
Edge
Detector
Event Detector
1
Event detection on line 0
0
PIO_AIMER[0]
PIO_AIMMR[0]
PIO_AIMDR[0]
31.5.10.1Example
If generating an interrupt is required on the lines below, the configuration required is described in Section 31.5.10.2
”Interrupt Mode Configuration”, Section 31.5.10.3 ”Edge or Level Detection Configuration” and Section 31.5.10.4
”Falling/Rising Edge or Low/High-Level Detection Configuration”:
 Rising edge on PIO line 0
 Falling edge on PIO line 1
 Rising edge on PIO line 2
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
567