SAM4S_14 Datasheet, PDF (563/1231 Pages) ATMEL Corporation – ARM-based Flash MCU

31.5.1 Pull-up and Pull-down Resistor Control
Each I/O line is designed with an embedded pull-up resistor and an embedded pull-down resistor. The pull-up
resistor can be enabled or disabled by writing to the Pull-up Enable register (PIO_PUER) or Pull-up Disable
register (PIO_PUDR), respectively. Writing to these registers results in setting or clearing the corresponding bit in
the Pull-up Status register (PIO_PUSR). Reading a one in PIO_PUSR means the pull-up is disabled and reading a
zero means the pull-up is enabled. The pull-down resistor can be enabled or disabled by writing the Pull-down
Enable register (PIO_PPDER) or the Pull-down Disable register (PIO_PPDDR), respectively. Writing in these
registers results in setting or clearing the corresponding bit in the Pull-down Status register (PIO_PPDSR).
Reading a one in PIO_PPDSR means the pull-up is disabled and reading a zero means the pull-down is enabled.
Enabling the pull-down resistor while the pull-up resistor is still enabled is not possible. In this case, the write of
PIO_PPDER for the relevant I/O line is discarded. Likewise, enabling the pull-up resistor while the pull-down
resistor is still enabled is not possible. In this case, the write of PIO_PUER for the relevant I/O line is discarded.
Control of the pull-up resistor is possible regardless of the configuration of the I/O line.
After reset, all of the pull-ups are enabled, i.e. PIO_PUSR resets at the value 0x0, and all the pull-downs are
disabled, i.e. PIO_PPDSR resets at the value 0xFFFFFFFF.
31.5.2 I/O Line or Peripheral Function Selection
When a pin is multiplexed with one or two peripheral functions, the selection is controlled with the Enable register
(PIO_PER) and the Disable register (PIO_PDR). The Status register (PIO_PSR) is the result of the set and clear
registers and indicates whether the pin is controlled by the corresponding peripheral or by the PIO Controller. A
value of zero indicates that the pin is controlled by the corresponding on-chip peripheral selected in the ABCD
Select registers (PIO_ABCDSR1 and PIO_ABCDSR2). A value of one indicates the pin is controlled by the PIO
Controller.
If a pin is used as a general-purpose I/O line (not multiplexed with an on-chip peripheral), PIO_PER and PIO_PDR
have no effect and PIO_PSR returns a one for the corresponding bit.
After reset, the I/O lines are controlled by the PIO Controller, i.e. PIO_PSR resets at one. However, in some
events, it is important that PIO lines are controlled by the peripheral (as in the case of memory chip select lines that
must be driven inactive after reset, or for address lines that must be driven low for booting out of an external
memory). Thus, the reset value of PIO_PSR is defined at the product level and depends on the multiplexing of the
device.
31.5.3 Peripheral A or B or C or D Selection
The PIO Controller provides multiplexing of up to four peripheral functions on a single pin. The selection is
performed by writing PIO_ABCDSR1 and PIO_ABCDSR2.
For each pin:
 The corresponding bit at level zero in PIO_ABCDSR1 and the corresponding bit at level zero in
PIO_ABCDSR2 means peripheral A is selected.
 The corresponding bit at level one in PIO_ABCDSR1 and the corresponding bit at level zero in
PIO_ABCDSR2 means peripheral B is selected.
 The corresponding bit at level zero in PIO_ABCDSR1 and the corresponding bit at level one in
PIO_ABCDSR2 means peripheral C is selected.
 The corresponding bit at level one in PIO_ABCDSR1 and the corresponding bit at level zero in
PIO_ABCDSR2 means peripheral D is selected.
Note that multiplexing of peripheral lines A, B, C and D only affects the output line. The peripheral input lines are
always connected to the pin input.
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
563