SAM4S_14 Datasheet, PDF (279/1231 Pages) ATMEL Corporation – ARM-based Flash MCU

 EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field ERSTL in the
Mode Register (RSTC_MR).
The software reset is entered if at least one of these bits is set by the software. All these commands can be
performed independently or simultaneously. The software reset lasts 3 Slow Clock cycles.
The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master
Clock (MCK). They are released when the software reset is left, i.e., synchronously to SLCK.
If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field ERSTL. However, the
resulting falling edge on NRST does not lead to a User Reset.
If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field RSTTYP of the
Status Register (RSTC_SR). Other Software Resets are not reported in RSTTYP.
As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Progress) is set in the
RSTC_SR. It is cleared as soon as the software reset is left. No other software reset can be performed while the
SRCMP bit is set, and writing any value in the RSTC_CR has no effect.
Figure 14-5. Software Reset
SLCK
MCK
Write RSTC_CR
proc_nreset
if PROCRST=1
RSTTYP
periph_nreset
if PERRST=1
NRST
(nrst_out)
if EXTRST=1
SRCMP in RSTC_SR
Any
Freq.
Resynch. Processor Startup
1 cycle
= 2 cycles
Any
XXX
0x3 = Software Reset
EXTERNAL RESET LENGTH
8 cycles (ERSTL=2)
14.4.4.5 Watchdog Reset
The Watchdog Reset is entered when a watchdog fault occurs. This state lasts three Slow Clock cycles.
When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in the WDT_MR:
 If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST line is also
asserted, depending on the programming of the field ERSTL. However, the resulting low level on NRST
does not result in a User Reset state.
 If WDRPROC = 1, only the processor reset is asserted.
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
279