SAM4S_14 Datasheet, PDF (1160/1231 Pages) ATMEL Corporation – ARM-based Flash MCU

The dynamic performances are the 12-bit mode values, reduced by 12 dB.
Low Voltage Supply
The ADC performs in 10-bit mode or in 12-bit mode. Working at low voltage (VDDIN or/and V_ADVREF) between 2
and 2.4V is subject to the following restrictions:
 The field IBCTL must be 00 to reduce the biasing of the ADC under low voltage. See Section 44.8.1.1 “ADC
Bias Current”.
 In 10-bit mode, the ADC clock should not exceed 5 MHz (max signal bandwidth is 250 kHz).
 In 12-bit mode, the ADC clock should not exceed 2 MHz (max signal bandwidth is 100 kHz).
44.8.5.3 ADC Channel Input Impedance
Figure 44-16. Input Channel Model
Single Ended model
Zin
Ron
Zin
Cin
Differential model
Ron
Cin
gnd
Ron
where:
 Z_IN is input impedance in single-ended or differential mode
 C_IN = 1 to 8 pF +/-20% depending on the gain value and mode (SE or DIFF); temperature dependency is
negligible
 R_ON is typical 2 kΩ and 8 kΩ max (worst case process and high temperature)
 R_ON is negligible regarding the value of Z_IN
The following formula is used to calculate input impedance:
Z_IN
=
---------1----------
f_S × C_IN
where:
 f_S is the sampling frequency of the ADC channel
 Typ values are used to compute ADC input impedance Z_IN
Table 44-52. Input Capacitance Values
Gain Selection
Single-ended
0.5
N/A⁽¹⁾
Differential
2 pF
1160
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14