SAM4CM_14 Datasheet, PDF (482/1177 Pages) ATMEL Corporation – Atmel | SMART ARM-based Flash MCU

The use of undefined length 8-beat bursts or less is discouraged since this may decrease the overall bus
bandwidth due to arbitration and slave latencies at each first access of a burst.
However, if the usual length of undefined length bursts is known for a master, it is recommended to configure the
ULBT according to this length.
This selection can be done through the ULBT field of the Master Configuration registers (MATRIX_MCFG).
26.7.1.2 Slot Cycle Limit Arbitration
The Bus Matrix contains specific logic to break long accesses, such as very long bursts on a very slow slave (e.g.,
an external low speed memory). At each arbitration time, a counter is loaded with the value previously written in
the SLOT_CYCLE field of the related Slave Configuration register (MATRIX_SCFG) and decreased at each clock
cycle. When the counter elapses, the arbiter has the ability to re-arbitrate at the end of the current AHB bus access
cycle.
Unless a master has a very tight access latency constraint, which could lead to data overflow or underflow due to a
badly undersized internal FIFO with respect to its throughput, the Slot Cycle Limit should be disabled
(SLOT_CYCLE = 0) or set to its default maximum value in order not to inefficiently break long bursts performed by
some Atmel masters.
In most cases, this feature is not needed and should be disabled for power saving.
Warning: This feature cannot prevent any slave from locking its access indefinitely.
26.7.2 Arbitration Priority Scheme
The Bus Matrix arbitration scheme is organized in priority pools. The corresponding access criticality class is
assigned to each priority pool as shown in the “Latency Quality of Service” column in Table 26-7. Latency Quality
of Service is determined through the Bus Matrix user interface. See Section 26.9.3 “Bus Matrix Priority Registers A
For Slaves” for details.
Table 26-7. Arbitration Priority Pools
Priority Pool Latency Quality of Service
3
Latency Critical
2
Latency Sensitive
1
Bandwidth Sensitive
0
Background Transfers
Round-robin priority is used in the highest and lowest priority pools 3 and 0, whereas fixed level priority is used
between priority pools and in the intermediate priority pools 2 and 1. See Section 26.7.2.2 “Round-robin
Arbitration”.
For each slave, each master is assigned to one of the slave priority pools through the Latency Quality of Service
inputs or through the priority registers for slaves (MxPR fields of MATRIX_PRAS and MATRIX_PRBS). When
evaluating master requests, this priority pool level always takes precedence.
After reset, most of the masters belong to the lowest priority pool (MxPR = 0, Background Transfer) and, therefore,
are granted bus access in a true round-robin order.
The highest priority pool must be specifically reserved for masters requiring very low access latency. If more than
one master belongs to this pool, they will be granted bus access in a biased round-robin manner which allows tight
and deterministic maximum access latency from AHB bus requests. In the worst case, any currently occurring
high-priority master request will be granted after the current bus master access has ended and other high priority
pool master requests, if any, have been granted once each.
The lowest priority pool shares the remaining bus bandwidth between AHB Masters.
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SAM4CM Series [DATASHEET]
Atmel-11203C-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-Datasheet_06-Oct-14