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AT91SAM9261S_14 Datasheet, PDF (424/709 Pages) ATMEL Corporation – Incorporates the ARM926EJ-S ARM Thumb Processor | |||
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AT91SAM9261S
⢠RSTSTA: Reset Status Bits
0: No effect.
1: Resets the status bits PARE, FRAME, OVREand RXBRK in US_CSR.
⢠STTBRK: Start Break
0: No effect.
1: Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been trans-
mitted. No effect if a break is already being transmitted.
⢠STPBRK: Stop Break
0: No effect.
1: Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods.
No effect if no break is being transmitted.
⢠STTTO: Start Time-out
0: No effect.
1: Starts waiting for a character before clocking the time-out counter. Resets the status bit TIMEOUT in US_CSR.
⢠SENDA: Send Address
0: No effect.
1: In Multidrop Mode only, the next character written to the US_THR is sent with the address bit set.
⢠RSTIT: Reset Iterations
0: No effect.
1: Resets ITERATION in US_CSR. No effect if the ISO7816 is not enabled.
⢠RSTNACK: Reset Non Acknowledge
0: No effect
1: Resets NACK in US_CSR.
⢠RETTO: Rearm Time-out
0: No effect
1: Restart Time-out
⢠RTSEN: Request to Send Enable
0: No effect.
1: Drives the pin RTS to 0.
⢠RTSDIS: Request to Send Disable
0: No effect.
1: Drives the pin RTS to 1.
6242EâATARMâ11-Sep09
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