AT91SAM9261S_14 Datasheet, PDF (378/709 Pages) ATMEL Corporation – Incorporates the ARM926EJ-S ARM Thumb Processor

31.6.6
Read/Write Flowcharts
The following flowcharts shown in Figure 31-13, Figure 31-14 on page 379, Figure 31-15 on
page 380, Figure 31-16 on page 381, Figure 31-17 on page 382 and Figure 31-18 on page 383
give examples for read and write operations. A polling or interrupt method can be used to check
the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be
configured first.
Figure 31-13. TWI Write Operation with Single Data Byte without Internal Address
BEGIN
Set TWI clock
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
(Needed only once)
Set the Control register:
- Master enable
TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address (DADR)
- Transfer direction bit
Write ==> bit MREAD = 0
Load Transmit register
TWI_THR = Data to send
Read Status register
No
TXRDY = 1?
Yes
Read Status register
No
TXCOMP = 1?
Yes
Transfer finished
378 AT91SAM9261S
6242E–ATARM–11-Sep09