AT91SAM9261S_14 Datasheet, PDF (212/709 Pages) ATMEL Corporation – Incorporates the ARM926EJ-S ARM Thumb Processor

AT91SAM9261S
The SDRAM device must remain in self-refresh mode for a minimum period of t_RAS and may
remain in self-refresh mode for an indefinite period. This is described in Figure 23-6.
Figure 23-6. Self-refresh Mode Behavior
Write
SDRAMC_SRR
SDRAMC_A[12:0]
SRCB = 1
Self Refresh Mode
T_XSR = 3
Row
SDCK
SDCKE
SDCS
RAS
CAS
SDWE
Access Request
to the SDRAM Controller
23.5.5.2
Low-power Mode
This mode is selected by programming the LPCB field to 2 in the SDRAMC Low Power Register.
Power consumption is greater than in self-refresh mode. All the input and output buffers of the
SDRAM device are deactivated except SDCKE, which remains low. In contrast to self-refresh
mode, the SDRAM device cannot remain in low-power mode longer than the refresh period (64
ms for a whole device refresh operation). As no auto-refresh operations are performed by the
SDRAM itself, the SDRAM Controller carries out the refresh operation. The exit procedure is
faster than in self-refresh mode.
This is described in Figure 23-7.
6242E–ATARM–11-Sep09
212