AT91SAM9261S_14 Datasheet, PDF (161/709 Pages) ATMEL Corporation – Incorporates the ARM926EJ-S ARM Thumb Processor

AT91SAM9261S
22. Static Memory Controller (SMC)
22.1 Overview
The Static Memory Controller (SMC) generates the signals that control the access to the exter-
nal memory devices or peripheral devices. It has 8 Chip Selects and a 26-bit address bus. The
32-bit data bus can be configured to interface with 8-, 16-, or 32-bit external devices. Separate
read and write control signals allow for direct memory and peripheral interfacing. Read and write
signal waveforms are fully parametrizable.
The SMC can manage wait requests from external devices to extend the current access. The
SMC is provided with an automatic slow clock mode. In slow clock mode, it switches from user-
programmed waveforms to slow-rate specific waveforms on read and write signals. The SMC
supports asynchronous burst read in page mode access for page size up to 32 bytes.
22.2 I/O Lines Description
Table 22-1. I/O Line Description
Name
Description
NCS[7:0]
Static Memory Controller Chip Select Lines
NRD
Read Signal
NWR0/NWE
Write 0/Write Enable Signal
A0/NBS0
Address Bit 0/Byte 0 Select Signal
NWR1/NBS1
Write 1/Byte 1 Select Signal
A1/NWR2/NBS2
Address Bit 1/Write 2/Byte 2 Select Signal
NWR3/NBS3
Write 3/Byte 3 Select Signal
A[25:2]
Address Bus
D[31:0]
Data Bus
NWAIT
External Wait Signal
Type
Output
Output
Output
Output
Output
Output
Output
Output
I/O
Input
Active Level
Low
Low
Low
Low
Low
Low
Low
Low
22.3 Multiplexed Signals
Table 22-2. Static Memory Controller (SMC) Multiplexed Signals
Multiplexed Signals
Related Function
NWR0
NWE
Byte-write or byte-select access, see “Byte Write or Byte Select Access” on page 163
A0
NBS0
8-bit or 16-/32-bit data bus, see “Data Bus Width” on page 163
NWR1
NBS1
Byte-write or byte-select access see “Byte Write or Byte Select Access” on page 163
A1
NWR2
NBS2
8-/16-bit or 32-bit data bus, see “Data Bus Width” on page 163.
Byte-write or byte-select access, see “Byte Write or Byte Select Access” on page 163
NWR3
NBS3
Byte-write or byte-select access see “Byte Write or Byte Select Access” on page 163
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