AT91SAM9261S_14 Datasheet, PDF (243/709 Pages) ATMEL Corporation – Incorporates the ARM926EJ-S ARM Thumb Processor

AT91SAM9261S
Figure 26-1. Master Clock Controller
PMC_MCKR
CSS
PMC_MCKR
PRES
SLCK
MAINCK
PLLACK
PLLBCK
Master Clock
Prescaler
PMC_MCKR
MDIV
Master
Clock
Divider
MCK
To the Processor
Clock Controller (PCK)
26.3
Processor Clock Controller
The PMC features a Processor Clock Controller (PCK) that implements the Processor Idle
Mode. The Processor Clock can be disabled by writing the System Clock Disable Register
(PMC_SCDR). The status of this clock (at least for debug purposes) can be read in the System
Clock Status Register (PMC_SCSR).
The Processor Clock PCK is enabled after a reset and is automatically re-enabled by any
enabled interrupt. The Processor Idle Mode is achieved by disabling the Processor Clock and
entering Wait for Interrupt Mode. The Processor Clock is automatically re-enabled by any
enabled fast or normal interrupt, or by the reset of the product.
Note:
The ARM Wait for Interrupt mode is entered with CP15 coprocessor operation. Refer to the Atmel
application note, Optimizing Power Consumption for AT91SAM9261-based Systems, lit. number
6217.
When the Processor Clock is disabled, the current instruction is finished before the clock is
stopped, but this does not prevent data transfers from other masters of the system bus.
26.4
USB Clock Controller
The USB Source Clock is always generated from the PLL B output. If using the USB, the user
must program the PLL to generate a 48 MHz, a 96 MHz or a 192 MHz signal with an accuracy of
± 0.25% depending on the USBDIV bit in CKGR_PLLBR (see Figure 26-2).
When the PLL B output is stable, i.e., the LOCKB is set:
• The USB device clock can be enabled by setting the UDP bit in PMC_SCER. To save power
on this peripheral when it is not used, the user can set the UDP bit in PMC_SCDR. The UDP
bit in PMC_SCSR gives the activity of this clock. The USB device port require both the 48
MHz signal and the Master Clock. The Master Clock may be controlled via the Master Clock
Controller.
Figure 26-2. USB Clock Controller
USBDIV
USB
Source
Clock
Divider
/1,/2,/4
UDP
UDP Clock (UDPCK)
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