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U3742BM Datasheet, PDF (4/32 Pages) ATMEL Corporation – UHF ASK/FSK RECEIVER
Pin Description (Continued)
Pin
Symbol Function
Selecting 433.92 MHz/315 MHz
16
MODE Low: 4.90625 MHz (USA)
High: 6.76438 (Europe)
17
RSSI
Output of the RSSI amplifier
18
TEST Test pin, during operation at GND
Enables the polling mode
19
ENABLE Low: polling mode off (sleep mode)
High: polling mode on (active mode)
20
DATA
Data output/configuration input
RF Front End
The RF front end of the receiver is a heterodyne configuration that converts the input
signal into a 1 MHz IF signal. According to Figure 2 on page 2, the front end consists of
an LNA (low noise amplifier), LO (local oscillator), a mixer and an RF amplifier.
The LO generates the carrier frequency for the mixer via a PLL synthesizer. The XTO
(crystal oscillator) generates the reference frequency fXTO. The VCO (voltage-controlled
oscillator) generates the drive voltage frequency fLO for the mixer. fLO is dependent on
the voltage at pin LF. fLO is divided by a factor of 64. The divided frequency is compared
to fXTO by the phase frequency detector. The current output of the phase frequency
detector is connected to a passive loop filter and thereby generates the control voltage
VLF for the VCO. By means of that configuration, VLF is controlled in a way that fLO/64 is
equal to fXTO. If fLO is determined, fXTO can be calculated using the following formula:
fXTO = fLO/64
The XTO is a one-pin oscillator that operates at the series resonance of the quartz crys-
tal. According to Figure 4, the crystal should be connected to GND via the capacitor CL.
The value of that capacitor is recommended by the crystal supplier. The value of CL
should be optimized for the individual board layout to achieve the exact value of fXTO and
hereby of fLO. When designing the system in terms of receiving bandwidth, the accuracy
of the crystal and the XTO must be considered.
Figure 4. PLL Peripherals
VS
DVCC
CL
XTO
LFGND
LF
R1 = 820 Ω
C9 = 4.7 nF
C10 = 1 nF
VS
LFVCC
R1
C10
C9
4 U3742BM
4735A–RKE–11/03