U3742BM Datasheet, PDF (17/32 Pages) ATMEL Corporation – UHF ASK/FSK RECEIVER

U3742BM
The minimum time period between two edges of the data signal is limited to
t_ee ³ T_{DATA_min}. This implies an efficient suppression of spikes at the DATA output. At the
same time, it limits the maximum frequency of edges at DATA. This eases the interrupt
handling of a connected microcontroller. T_{DATA_min} is to some extent affected by the pre-
ceding edge-to-edge time interval tee as illustrated in Figure 19. If t_ee is in between the
specified bit check limits, the following level is frozen for the time period
T_{DATA_min} = tmin1, in case of t_ee being outside that bit check limits T_{DATA_min} = tmin2 is
the relevant stable time period.
The maximum time period for DATA to be Low is limited to T_{DATA_L_max}. This function
ensures a finite response time during programming or switching off the receiver via pin
DATA. T_{DATA_L_max} is thereby longer than the maximum time period indicated by the
transmitter data stream. Figure 20 gives an example where Dem_out remains Low after
the receiver is in receiving mode.
Figure 18. Synchronization of the Demodulator Output
Clock bit check
Counter
T_XClk
Dem_out
DATA
t_ee
Figure 19. Debouncing of the Demodulator Output
Dem_out
DATA
Lim_min ≤ CV_Lim < Lim_max
t_ee
tmin1
CV_Lim < Lim_min or CV_Lim ≥ Lim_max
t_ee
Figure 20. Steady L State Limited DATA Output Pattern after Transmission
Enable IC
tmin2
Bit check
Dem_out
DATA
Startup mode
Bit check mode
Receiving mode
tmin2
t_{DATA_L_max}
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4735A–RKE–11/03