U3742BM Datasheet, PDF (14/32 Pages) ATMEL Corporation – UHF ASK/FSK RECEIVER

Figure 13. Polling Mode Flow Chart
Sleep mode:
All circuits for signal processing
are disabled. Only XTO and
polling logic are enabled.
I_S = I_Soff
T_Sleep = Sleep × X_Sleep × 1024 × T_Clk
Start-up mode:
The signal processing circuits are
enabled. After the start-up time
(T_Startup) all circuits are in stable
condition and ready to receive.
I_S = I_Son
T_Startup
Sleep:
5-bit word defined by Sleep0 to
Sleep4 in OPMODE register
X_Sleep:
T_CLK:
T_Startup:
Extension factor defined by
XSleep_Std and XSleep_Temp
according to Table 8
Basic clock cycle defined by f_XTO and pin MODE
Is defined by the selected baud rate range and T_Clk.
The baud rate range is defined by Baud0 and Baud1
in the OPMODE register.
Bit check mode:
The incoming data stream is
analyzed. If the timing indicates a
valid transmitter signal, the receiver
is set to receiving mode. Otherwise
it is set to Sleep mode.
I_S = I_Son
T_Bitcheck
NO
Bit check
OK ?
YES
Receiving mode:
The receiver is turned on permanently
and passes the data stream to the
connected microcontroller. It can be set
to Sleep mode through an OFF
command via pin DATA or ENABLE.
I_S = I_Son
OFF command
T_Bitcheck :
Depends on the result of the bit check
If the bit check is ok, T_bitcheck depends on
the number of bits to be checked (N_Bitcheck)
and on the utilized data rate.
If the bit check fails, the average time period for
that check depends on the selected baud rate
range and on T_Clk. The baud rate is defined by
Baud0 and Baud1 in the OPMODE register.
14 U3742BM
4735A–RKE–11/03