U3742BM Datasheet, PDF (15/32 Pages) ATMEL Corporation – UHF ASK/FSK RECEIVER

U3742BM
Figure 14. Timing Diagram for Complete Successful Bit Check
(Number of checked bits: 3)
Bit check ok
Enable IC
Bit check
Dem_out
DATA
Startup mode
1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit
Bit check mode
Receiving mode
Figure 15. Timing Diagram During Bit Check
(Lim_min = 14, Lim_max = 24)
Bit check ok
Bit check ok
Enable IC
Bit check
Dem_out
T_Startup
1/2 Bit
1/2 Bit
1/2 Bit
Bit check counter
0
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 1011121314151617 18 1 2 3 4 5 6 7 8 9 1011121314 15 1 2 3 4
T_XCLK
Figure 16. Timing Diagram for Failed Bit Check (Condition: CV_Lim < Lim_min)
(Lim_min = 14, Lim_max = 24)
Enable IC
Bit check failed (CV_Lim < Lim_min)
Bit check
Dem_out
Bit check counter
1/2 Bit
0
1 2 3 4 5 6 1 2 3 4 5 6 7 8 9 101112
Startup mode
Bit check mode
0
Sleep mode
15
4735A–RKE–11/03