U3742BM Datasheet, PDF (11/32 Pages) ATMEL Corporation – UHF ASK/FSK RECEIVER

U3742BM
Basic Clock Cycle of the
Digital Circuitry
The complete timing of the digital circuitry and the analog filtering is derived from one
clock. According to Figure 11, this clock cycle T_Clk is derived from the crystal oscillator
(XTO) in combination with a divider. The division factor is controlled by the logical state
at pin MODE. According to section “RF Front End” on page 4, the frequency of the crys-
tal oscillator (f_XTO) is defined by the RF input signal (f_RFin) which also defines the
operating frequency of the local oscillator (f_LO).
Figure 11. Generation of the Basic Clock Cycle
T_CLK
Divider
:14/:10
f_XTO
XTO
MODE
L : USA(:10)
16
H: Europe(:14)
DVCC
15
XTO
14
Pin MODE can now be set in accordance with the desired clock cycle T_Clk. T_Clk controls
the following application-relevant parameters:
• Timing of the polling circuit including bit check
• Timing of the analog and digital signal processing
• Timing of the register programming
• Frequency of the reset marker
• IF filter center frequency (f_IF0)
Most applications are dominated by two transmission frequencies: f_Send = 315 MHz is
mainly used in the USA, f_Send = 433.92 MHz in Europe. In order to ease the usage of all
T_Clk-dependent parameters, the electrical characteristics display three conditions for
each parameter.
• Application USA (f_XTO = 4.90625 MHz, MODE = L, T_Clk = 2.0383 µs)
• Application Europe (f_XTO = 6.76438 MHz, MODE = H, T_Clk = 2.0697 µs)
• Other applications (T_Clk is dependent on f_XTO and on the logical state of pin MODE.
The electrical characteristic is given as a function of T_Clk).
The clock cycle of some function blocks depends on the selected baud rate range
(BR_Range) which is defined in the OPMODE register. This clock cycle T_XClk is defined
by the following formulas for further reference:
BR_Range =
BR_Range0:
BR_Range1:
BR_Range2:
BR_Range3:
T_XClk = 8 ´ T_Clk
T_XClk = 4 ´ T_Clk
T_XClk = 2 ´ T_Clk
T_XClk = 1 ´ T_Clk
11
4735A–RKE–11/03