ATA6616_12 Datasheet, PDF (17/308 Pages) ATMEL Corporation – 8K/16K Flash Microcontroller with LIN Transceiver, 5V Regulator and Watchdog

Atmel ATA6616/ATA6617
3.6 Watchdog
The watchdog anticipates a trigger signal from the microcontroller at the NTRIG (negative
edge) input within a time window of T_wd. The trigger signal must exceed a minimum time
t_trigmin > 200ns. If a triggering signal is not received, a reset signal will be generated at output
NRES. After a watchdog reset, the IC starts with the lead time. The timing basis of the watch-
dog is provided by the internal oscillator. Its time period, T_osc, is adjustable via the external
resistor R_{wd_osc} (34kΩ to 120kΩ).
During Silent or Sleep Mode the watchdog is switched off to reduce current consumption.
The minimum time for the first watchdog pulse is required after the undervoltage reset at
NRES disappears. It is defined as lead time t_d. After wake up from Sleep or Silent Mode, the
lead time t_d starts with the negative edge of the RXD output.
3.6.1
Typical Timing Sequence with R_{WD_OSC} = 51kΩ
The trigger signal T_wd is adjustable between 20ms and 64ms using the external resistor
R_{WD_OSC}.
For example, with an external resistor of R_{WD_OSC} = 51kΩ ±1%, the typical parameters of the
watchdog are as follows:
t_osc = 0.405 × R_{WD_OSC} – 0.0004 × (R_{WD_OSC})² (R_{WD_OSC} in kΩ; t_osc in µs)
t_OSC = 19.6µs due to 51kΩ
t_d = 7895 × 19.6µs = 155ms
t₁ = 1053 × 19.6µs = 20.6ms
t₂ = 1105 × 19.6µs = 21.6ms
t_nres = constant = 4 ms
After ramping up the battery voltage, the 5V regulator is switched on. The reset output NRES
stays low for the time t_reset (typically 4ms), then it switches to high, and the watchdog waits for
the trigger sequence from the microcontroller. The lead time, t_d, follows the reset and is
t_d = 155ms. In this time, the first watchdog pulse from the microcontroller is required. If the trig-
ger pulse NTRIG occurs during this time, the time t₁ starts immediately. If no trigger signal
occurs during the time t_d, a watchdog reset with t_NRES = 4ms will reset the microcontroller after
t_d = 155ms. The times t₁ and t₂ have a fixed relationship between each other. A triggering sig-
nal from the microcontroller is anticipated within the time frame of t₂ = 21.6ms. To avoid false
triggering from glitches, the trigger pulse must be longer than t_TRIG,min > 200ns. This slope
serves to restart the watchdog sequence. If the triggering signal fails in this open window t₂,
the NRES output will be drawn to ground. A triggering signal during the closed window t₁
immediately switches NRES to low.
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