ATA6616_12 Datasheet, PDF (149/308 Pages) ATMEL Corporation – 8K/16K Flash Microcontroller with LIN Transceiver, 5V Regulator and Watchdog

Atmel ATA6616/ATA6617
4.13.9.3
Fast PWM Mode
The fast Pulse Width Modulation or fast PWM mode (WGM13:0 = 5, 6, 7, 14, or 15) provides a
high frequency PWM waveform generation option. The fast PWM differs from the other PWM
options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts
from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1A/B) is set
on the compare match between TCNT1 and OCR1A/B, and cleared at TOP. In inverting Com-
pare Output mode output is cleared on compare match and set at TOP. Due to the
single-slope operation, the operating frequency of the fast PWM mode can be twice as high as
the phase correct and phase and frequency correct PWM modes that use dual-slope opera-
tion. This high frequency makes the fast PWM mode well suited for power regulation,
rectification, and DAC applications. High frequency allows physically small sized external
components (coils, capacitors), hence reduces total system cost.
The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or
OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the
maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be
calculated by using the following equation:
R_FPWM
=
-^l-^o---^g----⁽--^T----^O-----^P-----+-----¹----⁾
log ( 2 )
In fast PWM mode the counter is incremented until the counter value matches either one of
the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 5, 6, or 7), the value in ICR1
(WGM13:0 = 14), or the value in OCR1A (WGM13:0 = 15). The counter is then cleared at the
following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure
4-51. The figure shows fast PWM mode when OCR1A or ICR1 is used to define TOP. The
TCNT1 value is in the timing diagram shown as a histogram for illustrating the single-slope
operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal
line marks on the TCNT1 slopes represent compare matches between OCR1A/B and TCNT1.
The OC1A/B interrupt flag will be set when a compare match occurs.
Figure 4-51. Fast PWM Mode, Timing Diagram
OCRnx/TOP Update and
TOVn Interrupt Flag Set and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
TCNTn
OCnxi
OCnxi
Period
1
2
3
4
56
7
(COMnx1:0 = 2)
(COMnx1:0 = 3)
8
9132F–AUTO–02/12
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