ATA6616_12 Datasheet, PDF (124/308 Pages) ATMEL Corporation – 8K/16K Flash Microcontroller with LIN Transceiver, 5V Regulator and Watchdog

4.11.11 8-bit Timer/Counter Register Description
4.11.11.1
Timer/Counter0 Control Register A – TCCR0A
Bit
7
6
5
4
3
2
1
0
COM0A1 COM0A0
–
–
–
–
WGM01 WGM00 TCCR0A
Read/Write
R/W
R/W
R
R
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
• Bit 7:6 – COM0A1:0: Compare Match Output Mode A
These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0
bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is con-
nected to. However, note that the Data Direction Register (DDR) bit corresponding to OC0A
pin must be set in order to enable the output driver.
When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the
WGM01:0 bit setting. Table 4-30 shows the COM0A1:0 bit functionality when the WGM01:0
bits are set to a normal or CTC mode (non-PWM).
Table 4-30.
COM0A1
0
0
1
1
Compare Output Mode, non-PWM Mode
COM0A0 Description
0
Normal port operation, OC0A disconnected.
1
Toggle OC0A on Compare Match.
0
Clear OC0A on Compare Match.
1
Set OC0A on Compare Match.
Table 4-31 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM
mode.
Table 4-31. Compare Output Mode, Fast PWM Mode⁽¹⁾
COM0A1
COM0A0 Description
0
0
Normal port operation, OC0A disconnected.
0
1
Clear OC0A on Compare Match.
1
0
Set OC0A at BOTTOM (non-inverting mode).
Set OC0A on Compare Match.
1
1
Clear OC0A at BOTTOM (inverting mode).
Note:
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the
Compare Match is ignored, but the set or clear is done at TOP. See Section 4.11.7.3 “Fast
PWM Mode” on page 117 for more details.
124 Atmel ATA6616/ATA6617
9132F–AUTO–02/12