ATR2406_14 Datasheet, PDF (16/26 Pages) ATMEL Corporation – Low-IF 2.4-GHz ISM Transceiver

Table 8-9. Description of the Conditions/States
Condition
C1
C2
C3
C4
C5
Description
Power down
ATR2406 is switched off and the supply current is lower than 1µA.
Power up
ATR2406 is powered up by toggling PU_REG and PU_TRX to high.
PU_REG enables the external AUX regulator transistor including VCO regulator. PU_TRX
enables internal blocks like the PLL and the VCO.
Depending on the value of the external capacitors (for example, at the AUX regulator, if one is
used), it is necessary to wait at least 40µs until the different supply voltages have settled.
Programming
The internal register of the ATR2406 is programmed via the three-wire interface. At TX, this is just
the PLL (transmit channel) and the deviation (Gaussian filter).
At RX, this is just the PLL (receive channel) and, if the clock recovery is used, also the bits to
enable this option. At the start of the three-wire programming, the enable signal is toggled from
high to low to enable clocking the data into the internal register. When the enable signal rises
again to high, the programmed data is latched. This is the time point at which the settling of the
PLL starts. It is necessary to wait the settling time of 200µs so that the VCO frequency is stable.
The reference clock needs to be applied to ATR2406 for at least the time when the PLL is in
operation, which is the programming state (C3) and the active slot (C4, C5). Out of the reference
clock, several internal signals are also derived, for example, the Gaussian filter circuitry and
TX_DATA sampling.
This is the receive slot where the transmit burst is received and data as well as recovered clock
are available.
This is the active transmit slot. As soon as TX_DATA is applied to ATR2406, the signal nOLE
toggles to low which enables modulation in open-loop mode.
The preamble (1-0-1-0 pattern) should start being sent at the start of TX_ON.
8.10 Received Signal Strength Indication (RSSI)
The RSSI is given as an analog voltage at the RSSI pin. A typical plot of the RSSI value is shown in Figure 8-4.
Figure 8-4. Typical RSSI Value versus Input Power
2.5
2.0
1.5
1.0
0.5
0
-130
-110
-90
-70
-50
-30
RF Level (dBm)
-10
10
16 ATR2406 [DATASHEET]
4779Q–ISM–09/14