ATR2406_14 Datasheet, PDF (14/26 Pages) ATMEL Corporation – Low-IF 2.4-GHz ISM Transceiver

8.8 Serial Programming Bus
The transceiver is programmed by the SPI (CLOCK, DATA and ENABLE).
After setting the enable signal to low, the data is transferred bit by bit into the shift register on the rising edge of the clock
signal, starting with the MSBit. When the enable signal has returned to high, the programmed information is active.
Additional leading bits are ignored and there is no check made of how many clock pulses arrived during enable low.
The programming of the transceiver is done by a 16-bit or 25-bit data word (for the RX clock recovery mode).
8.9 3-wire Bus Timing
Figure 8-2. 3-wire Bus Protocol Timing Diagram
DATA
CLOCK
ENABLE
TL
TPER
TS TC
TH
TEC TT
Table 8-8. 3-wire Bus Protocol Table
Description
Clock period
Set time data to clock
Hold time data to clock
Clock pulse width
Set time enable to clock
Hold time enable to data
Time between two protocols
Symbol
Minimum Value
Unit
TPER
100
ns
TS
20
ns
TH
20
ns
TC
60
ns
TL
100
ns
TEC
0
ns
TT
250
ns
14 ATR2406 [DATASHEET]
4779Q–ISM–09/14