ATR2406_14 Datasheet, PDF (12/26 Pages) ATMEL Corporation – Low-IF 2.4-GHz ISM Transceiver

8.4 RX Register Setting with Internal Clock Recovery
Recommended for 1.152Mbit/s data rate.
The output pin of the recovered clock is pin 6. The falling edge of the recovered clock signal samples the data signal.
MSB
Data bits
D24
D23
D22
D21
D20
D19
D18 D17 D16
1
0
1
0
0
0
0
0
0
LSB
Data bits
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2 D1
D0
0
0
X
X
X
X
X
0
RC
MC
SC
Note:
X values are not relevant and can be set to 0 or 1.
8.5 PLL Settings
RC, MC and SC bits control the synthesizer frequency as shown in Table 8-3, Table 8-4 on page 12 and Table 8-5 on page
13.
Formula for calculating the frequency:
TX frequency: f_ANT = 864kHz × (32 × S_MC + S_SC)
RX frequency: f_ANT = 864kHz × (32 × S_MC + S_SC – 1)
Table 8-3. PLL Settings of the Reference Counter Bit D7
RC (Reference Counter)
D7
0
1
CLK Reference
10.368MHz
13.824MHz
Table 8-4. PLL Settings of the Main Counter Bits D5 to D6
MC (Main Counter)
D6
D5
S_MC
0
0
86
0
1
87
1
0
88
1
1
89
12 ATR2406 [DATASHEET]
4779Q–ISM–09/14