AMD29F010B Datasheet, PDF (9/34 Pages) Advanced Micro Devices – 1 Megabit (128 K x 8-bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory

DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register it-
self does not occupy any addressable memory
location. The register is composed of latches that store
the commands, along with the address and data infor-
mation needed to execute the command. The contents
of the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function of
the device. The appropriate device bus operations
table lists the inputs and control levels required, and the
resulting output. The following subsections describe
each of these operations in further detail.
Table 1. Am29F010B Device Bus Operations
Operation
CE#
OE#
WE#
Addresses
(Note 1)
DQ0–DQ7
Read
Write
Standby
Output Disable
L
L
H
A_IN
D_OUT
L
H
L
A_IN
D_IN
V_CC ± 0.5 V
X
X
X
High-Z
L
H
H
X
High-Z
Hardware Reset
X
X
X
X
High-Z
Legend:
L = Logic Low = V_IL, H = Logic High = V_IH, V_ID = 12.0 ± 0.5 V, X = Don’t Care, A_IN = Addresses In, D_IN = Data In, D_OUT = Data Out
Notes:
1. Addresses are A16:A0.
2. The sector protect and sector unprotect functions must be implemented via programming equipment. See the “Sector Pro-
tection/Unprotection” section.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V_IL. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE# should
remain at V_IH.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory con-
tent occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard
microprocessor read cycles that assert valid addresses
on the device address inputs produce valid data on the
device data outputs. The device remains enabled for
read access until the command register contents are
altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to the Read Operations Timings diagram for
the timing waveforms. I_CC1 in the DC Characteristics
table represents the active current specification for
reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V_IL, and OE# to V_IH.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. The Sector Address Tables
indicate the address space that each sector occupies.
A “sector address” consists of the address bits required
to uniquely select a sector. See the “Command Defini-
tions” section for details on erasing a sector or the
entire chip.
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the “Autoselect Mode” and “Autoselect
Command Sequence” sections for more information.
I_CC2 in the DC Characteristics table represents the ac-
tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Am29F010B
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