AMD29F010B Datasheet, PDF (11/34 Pages) Advanced Micro Devices – 1 Megabit (128 K x 8-bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory

Table 3. Am29F010B Autoselect Codes (High Voltage Method)
Description
A16 A13
A8
A5
to to
to
to
CE# OE# WE# A14 A10 A9 A7 A6 A2 A1
Manufacturer ID: AMD
Device ID: Am29F010B
L
L
H
X
X V_ID X
L
X
L
L
L
H
X
X V_ID X
L
X
L
Sector Protection Verification
L
L
H SA X V_ID X
L
X
H
L = Logic Low = V_IL, H = Logic High = V_IH, SA = Sector Address, X = Don’t care.
DQ7
to
A0
DQ0
L
01h
H
20h
01h
(protected)
L
00h
(unprotected)
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The hard-
ware sector unprotection feature re-enables both
program and erase operations in previously protected
sectors.
Sector protection/unprotection must be implemented
using programming equipment. The procedure re-
quires a high voltage (V_ID) on address pin A9 and the
control pins. Details on this method are provided in a
supplement, publication number 22337. Contact an
AMD representative to obtain a copy of the appropriate
document.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Defi-
nitions table). In addition, the following hardware data
protection measures prevent accidental erasure or pro-
gramming, which might otherwise be caused by
spurious system level signals during V_CC power-up and
power-down transitions, or from system noise.
Low V_CC Write Inhibit
When V_CC is less than V_LKO, the device does not ac-
cept any write cycles. This protects data during V_CC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V_CC
is greater than V_LKO. The system must provide the
proper signals to the control pins to prevent uninten-
tional writes when V_CC is greater than V_LKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
V_IL, CE# = V_IH or WE# = V_IH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = V_IL and OE# = V_IH during power up, the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
Am29F010B
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