EP1AGX Datasheet, PDF (63/234 Pages) Altera Corporation – Section I. Arria GX Device Data Sheet

Chapter 2: Arria GX Architecture
2–57
TriMatrix Memory
Figure 2–49. M-RAM Row Unit Interface to Interconnect
C4 Interconnect
R4 and R24 Interconnects
M-RAM Block
LAB
16
Direct Link
Interconnects
Up to 16
dataout_a[ ]
Up to 28
datain_a[ ]
addressa[ ]
addr_ena_a
renwe_a
byteena_A[ ]
clocken_a
clock_a
aclr_a
Row Interface Block
M-RAM Block to
LAB Row Interface
Block Interconnect Region
Table 2–12 lists the input and output data signal connections along with the address
and control signal input connections to the row unit interfaces (L0 to L5 and R0 to R5).
Table 2–12. M-RAM Row Interface Unit Signals (Part 1 of 2)
Unit Interface Block
Input Signals
datain_a[14..0]
L0
byteena_a[1..0]
datain_a[29..15]
L1
byteena_a[3..2]
datain_a[35..30]
addressa[4..0]
addr_ena_a
L2
clock_a
clocken_a
renwe_a
aclr_a
addressa[15..5]
L3
datain_a[41..36]
Output Signals
dataout_a[11..0]
dataout_a[23..12]
dataout_a[35..24]
dataout_a[47..36]
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1