EP1AGX Datasheet, PDF (23/234 Pages) Altera Corporation – Section I. Arria GX Device Data Sheet

Chapter 2: Arria GX Architecture
2–17
Transceivers
Figure 2–16 shows misaligned channels before the channel aligner and the aligned
channels after the channel aligner.
Figure 2–16. Before and After the Channel Aligner
Lane 3
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Lane 2
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Lane 1
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Lane 0
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Lane 3
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Lane 2
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Lane 1
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Lane 0
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Rate Matcher
In asynchronous systems, the upstream transmitter and local receiver can be clocked
with independent reference clock sources. Frequency differences in the order of a few
hundred PPM can potentially corrupt the data at the receiver.
The rate matcher compensates for small clock frequency differences between the
upstream transmitter and the local receiver clocks by inserting or removing skip
characters from the inter packet gap (IPG) or idle streams. It inserts a skip character if
the local receiver is running a faster clock than the upstream transmitter. It deletes a
skip character if the local receiver is running a slower clock than the upstream
transmitter. The Quartus II software automatically configures the appropriate skip
character as specified in the IEEE 802.3 for GIGE mode and PCI-Express Base
Specification for PCI Express (PIPE) mode. The rate matcher is bypassed in Serial
RapidIO and must be implemented in the PLD logic array or external circuits
depending on your system design.
Table 2–5 lists the maximum frequency difference that the rate matcher can tolerate in
XAUI, PCI Express (PIPE), GIGE, and Basic functional modes.
Table 2–5. Rate Matcher PPM Tolerance
Function Mode
XAUI
PCI Express (PIPE)
GIGE
Basic
PPM
± 100
± 300
± 100
± 300
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1