EP1AGX Datasheet, PDF (53/234 Pages) Altera Corporation – Section I. Arria GX Device Data Sheet

Chapter 2: Arria GX Architecture
2–47
MultiTrack Interconnect
Figure 2–41. C4 Interconnect Connections (Note 1)
Row
Interconnect
C4 Interconnect
Drives Local and R4
Interconnects
up to Four Rows
C4 Interconnect
Driving Up
LAB
Adjacent LAB can
drive onto neighboring
LAB's C4 interconnect
Local
Interconnect
C4 Interconnect
Driving Down
Note to Figure 2–41:
(1) Each C4 interconnect can drive either up or down four rows.
C16 column interconnects span a length of 16 LABs and provide the fastest resource
for long column connections between LABs, TriMatrix memory blocks, DSP blocks,
and IOEs. C16 interconnects can cross M-RAM blocks and also drive to row and
column interconnects at every fourth LAB. C16 interconnects drive LAB local
interconnects via C4 and R4 interconnects and do not drive LAB local interconnects
directly. All embedded blocks communicate with the logic array similar to
LAB-to-LAB interfaces. Each block (that is, TriMatrix memory and DSP blocks)
connects to row and column interconnects and has local interconnect regions driven
by row and column interconnects. These blocks also have direct link interconnects for
fast connections to and from a neighboring LAB. All blocks are fed by the row LAB
clocks, labclk[5..0].
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1