EP1AGX Datasheet, PDF (46/234 Pages) Altera Corporation – Section I. Arria GX Device Data Sheet

2–40
Chapter 2: Arria GX Architecture
Adaptive Logic Modules
The other half of the ALMs in the LAB is available for implementing narrower fan-in
functions in normal mode. Carry chains that use the top four ALMs in the first LAB
carries into the top half of the ALMs in the next LAB within the column. Carry chains
that use the bottom four ALMs in the first LAB carries into the bottom half of the
ALMs in the next LAB within the column. Every other column of the LABs are
top-half bypassable, while the other LAB columns are bottom-half bypassable. For
more information about carry chain interconnect, refer to “MultiTrack Interconnect”
on page 2–44.
Shared Arithmetic Mode
In shared arithmetic mode, the ALM can implement a three-input add. In this mode,
the ALM is configured with four 4-input LUTs. Each LUT either computes the sum of
three inputs or the carry of three inputs. The output of the carry computation is fed to
the next adder (either to adder1 in the same ALM or to adder0 of the next ALM in
the LAB) using a dedicated connection called the shared arithmetic chain. This shared
arithmetic chain can significantly improve the performance of an adder tree by
reducing the number of summation stages required to implement an adder tree.
Figure 2–36 shows the ALM in shared arithmetic mode.
Figure 2–36. ALM in Shared Arithmetic Mode
shared_arith_in
carry_in
datae0
datac
datab
dataa
datad
datae1
4-Input
LUT
4-Input
LUT
4-Input
LUT
4-Input
LUT
DQ
reg0
To general or
local routing
To general or
local routing
DQ
reg1
To general or
local routing
To general or
local routing
carry_out
shared_arith_out
Note to Figure 2–36:
(1) Inputs dataf0 and dataf1 are available for register packing in shared arithmetic mode.
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation